In known VLSI electronic components, a significant factor in defining the power consumed by the chip is the power consumed by a clock driver circuit. Typically, such clock driver circuits are differential circuits in that they produce two different clock signals, with one such clock signal being the inverse of the other. Each of these drivers are connected by interconnections with a large number of circuits connected thereto. As such, a good deal of current is required to drive all the circuits receiving the differential clock signals. This is due to the capacitive nature of the load placed on the driver circuit by circuit capacitance as well as the interconnect wiring capacitance. Accordingly, the clock driver circuit must be capable of delivering a great deal of current to charge the capacitance associated with the load coupled thereto.
Various approaches have been tried to overcome problems associated with capacitive loading on clock driver circuits which increases the transition time for the clock signal to switch from one state to the opposite state (i.e., from high to low or from low to high). One approach has been to increase the number of clock driver circuits coupled in parallel to thereby reduce the loading on each clock driver. This approach, however, requires a large number of additional clock driver circuits to have any significant effect on the capacitive loading of each clock driver. When this is done, there is a corresponding increase in the chip area needed to provide clock signals which thereby reduces the number of active logic circuits and the like which can be designed into the circuit. Also, there is increased danger of clock skewing between the various clock circuits. In addition, it does not function in a way which will reduce the power requirements for the clock driver circuit.
A second approach to improving the switching speed for clock driver circuits has been to utilize a bipolar ECL circuit to act as the clock driver circuit. Due to the current handling capacity of a bipolar transistor, such circuits produce faster switching of clock states from one state to another than can be provided by a CMOS clock driver of conventional design. This approach, however, does require creating the bipolar circuit in an otherwise MOS design which does contribute to greater manufacturing complexity and may give rise to other problems associated with BiCMOS designs. It also does not function in a way to reduce the power requirements for the clock driver circuit.